HSA Floorplanning Design Contest

6th December 2017 - 19th December 2017 @ Politecnico di Milano

Contest description

Floorplanning is the process of choosing the best grouping and connectivity of logic in a design, and of manually placing blocks of logic in an FPGA, where the goal is to increase density, routability, or performance. The intent is to reduce route delays for selected logic by suggesting a better placement. A good floorplanning methodology can improve performance and help the placed and routed design meet timing.

Prof. Santambrogio and Prof. Miele, in the context of their PhD course “Advanced Topic on Heterogeneous Computing System” are organising, with Marco Rabozzi, the first Floorplanner Design Contest at Politecnico di Milano. Students attending the course are invited to participate, but participation is not mandatory.

The design contest will open on the 6th of December and will close on the 19th December at noon (strict submission deadline). During this period of time, participants will have the chance to attend some special tutoring sessions.

Each project / entry for the contest has to be realized by a single participant.

The introductory material on Floorplanning and on the floorplanning design contest is available at the following link: http://floorplanning-contest.necst.it/hsa-floorplanning-contest.pdf.

An example of a floorplanning algorithm that can be used as a starting example is available on github at: https://github.com/marcorabozzi/naive-floorplanner

Classes Timetable

Date Time Room (@ Politecnico) Topic
6th of December 2pm - 5pm Seminar Room @ Building 20, DEIB Introduction to FPGA Floorplanning and the design contest
12nd of December 9am - 12pm Basemenet @ Building 20, NECSTLab Meeting Room Tutoring session
14th of December 1pm - 3pm Basemenet @ Building 20, NECSTLab Meeting Room Tutoring session

Evaluation Criteria

Once logged to this website, the participants will have access to a set of problems of different levels of complexity. Each problem provides a description of the target FPGA, the design to be floorplanned and the parameters that define the objective function to be optimized for the given design. Each participant will have to devise his / her own floorplanning algorithm in order to try to find a floorplan that satisfies all the design constraints and optimizes the given objective function.

During the contest, the participants are allowed to perform multiple submissions. Each submission consists of two files:

  • An archive containing the code of the algorithm (no restrictions on the programming language)
  • An archive containing a set of txt files (formatted as specified in the introductory material) containing the solutions to one or more problems solved using the floorplanner.

After each submission, the system will verify all the provided solutions, compute the objective function for each floorplan and associate a score to the submission.

Each feasible floorplan will be assigned a score that is equal to the value of its objective function, whereas infeasible solutions do not incur any penalty. The score of the submission is equal to the sum of the best floorplans' scores of the solved problems (if two floorplans for the same problem are sent, only the best one is considered). The user's score is the highest score achieved across all the submissions.

At the end of the competition, both the quality of the solutions and the novelty / performance of the devised algorithm will be taken into account.

Please note that additional problems might be added during the contest.


The two winners of the contest will be selected for attending RAW workshop at IPDPS conference in Vancouver (21st - 22nd of May 2018) and in joining the NECSTLab delegation to attend the NECST Group Conference in San Francisco (22nd of May - 3rd of June 2018).

Register now!

To register for the contest, complete this form. Then, if you have not received the login credentials yet, send an email to marco dot rabozzi at polimi dot it with the subject "HSA Floorplanning Contest Registration" to ask for the credentials.